- Method and apparatus for creating circuit redundancy in programmable logic devices, Praveen K. Samudrala, Srinivas Katkoori, and Jeremy Ramos. US Patent No. 6,963,217.Abstract: A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.
