Publications

Journals – 19

  1. Evren Bozgeyikli, Andrew Raij, Srinivas Katkoori, Rajiv V. Dubey, “Locomotion in virtual reality for room scale tracked areas”. Int. J. Hum.-Comput. Stud. 122: 38-49 (2019)
  2. Lal Bozgeyikli, Evren Bozgeyikli, Srinivas Katkoori, Andrew Raij, Redwan Alqasemi, “Effects of Virtual Reality Properties on User Experience of Individuals with Autism”. TACCESS 11(4): 22:1-22:27 (2018)
  3. Lal Bozgeyikli, Andrew Raij, Srinivas Katkoori, Redwan Alqasemi, “A Survey on Virtual Reality for Individuals with Autism Spectrum Disorder: Design Considerations”. TLT 11(2): 133-151 (2018)
  4. Rekha Govindaraj, Swaroop Ghosh, Srinivas Katkoori, “CSRO-Based Reconfigurable True Random Number Generator Using RRAM”. IEEE Trans. VLSI Syst. 26(12): 2661-2670 (2018)
  5. Lal Bozgeyikli, Evren Bozgeyikli, Andrew Raij, Redwan Alqasemi, Srinivas Katkoori, Rajiv V. Dubey, “Vocational Rehabilitation of Individuals with Autism Spectrum Disorder with Virtual Reality”. TACCESS 10(2): 5:1-5:25 (2017)
  6. Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori, “State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores”. IEEE Trans. Computers 60(11): 1547-1560 (2011)
  7. Hariharan Sankaran, Srinivas Katkoori, “Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis”. IEEE Trans. VLSI Syst. 19(2): 217-226 (2011)
  8. Pradeep Fernando, Srinivas Katkoori, Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, “Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine”. IEEE Trans. Evolutionary Computation14(1): 133-149 (2010)
  9. Vyas Krishnan, Srinivas Katkoori, “TABS: Temperature-Aware Layout-Driven Behavioral Synthesis”. IEEE Trans. VLSI Syst. 18(12): 1649-1659 (2010)
  10. Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori, “A Framework for Power-Gating Functional Units in Embedded Microprocessors”. IEEE Trans. VLSI Syst. 17(11): 1640-1649 (2009)
  11. Vyas Krishnan, Srinivas Katkoori, “A genetic algorithm for the design space exploration of datapaths during high-level synthesis”. IEEE Trans. Evolutionary Computation10(3): 213-229 (2006)
  12. Suvodeep Gupta, Srinivas Katkoori, “Intrabus crosstalk estimation using word-level statistics”. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 469-478 (2005)
  13. Hao Li, Srinivas Katkoori, Wai-Kei Mak, “Power minimization algorithms for LUT-based FPGA technology mapping”. ACM Trans. Design Autom. Electr. Syst. 9(1): 33-51 (2004)
  14. Stelian Alupoaei, Srinivas Katkoori, “Ant colony system application to macrocell overlap removal”. IEEE Trans. VLSI Syst. 12(10): 1118-1123 (2004)
  15. Stelian Alupoaei, Srinivas Katkoori, “Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement”. VLSI Signal Processing 37(1): 151-163 (2004)
  16. Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy, “An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications”. ACM Trans. Design Autom. Electr. Syst. 7(1): 189-216 (2002)
  17. Stelian Alupoaei, Srinivas Katkoori, “Net-based force-directed macrocell placement for wirelength optimization”. IEEE Trans. VLSI Syst. 10(6): 824-835 (2002)
  18. Srinivas Katkoori, Ranga Vemuri, “Architectural Power Estimation Based on Behavior Level Profiling”. VLSI Design 1998(3): 255-270 (1998)
  19. Nand Kumar, Srinivas Katkoori, Leo Rader, Ranga Vemuri, “Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems”. IEEE Design & Test of Computers 12(3): 70-84 (1995)

Conferences – 71

  1.  S. A. Islam and S. Katkoori, “High-Level Synthesis of Key Based Obfuscated RTL Datapaths,” 2018 International Symposium on Quality of Electronic Design (ISQED). IEEE Link
  2. L. Bozgeyikli, E. Bozgeyikli, A. Raij, R. Alqasemi, S. Katkoori, and R. Dubey, “Vocational Rehabilitation of Individuals with Autism Spectrum Disorder with Virtual Reality,” To Appear In Proceedings of The 19th International ACM SIGACCESS Conference on Computers and Accessibility, 2017.
  3. L. Bozgeyikli, A. Raij, S. Katkoori, and R. Alqasemi, “Effects of Instruction Methods on User Experience in Virtual Reality Serious Games,” To Appear In Proceedings of The 19th International Conference on Human-Computer Interaction, 2017.
  4. E. Bozgeyikli, A. Raij, S. Katkoori, and R. Dubey, “Point & Teleport Locomotion Technique for Virtual Reality,” In Proceedings of the 2016 Annual ACM Symposium on Computer-Human Interaction in Play (CHI PLAY 2016), NY, USA, Pages(s): 205-216.
  5. S. Aditham, N. Ranganathan, and S. Katkoori, “LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems,” 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Orlando/Buena Vista, FL, USA, 2017, Page(s): 1259-1267.
  6. E. Bozgeyikli, A. Raij, S. Katkoori, and R. Dubey, “Locomotion in Virtual Reality for Individuals with Autism Spectrum Disorder,” In Proceedings of the
    2016 ACM Symposium on Spatial User Interaction (SUI \’16), New York, NY, USA, Page(s): 33-42.
  7. E. Bozgeyikli, L. Bozgeyikli, A. Raij, S. Katkoori, R. Alqasemi, and R. Dubey. “Virtual Reality Interaction Techniques for Individuals with Autism Spectrum Disorder: Design Considerations and Preliminary Results,” In Proceedings, Part II, of the 18th International Conference on Human-Computer Interaction. Interaction Platforms and Techniques – Volume 9732, Masaaki Kurosu (Ed.), Vol. 9732. Springer-Verlag New York, Inc., New York, NY, USA, Page(s): 127-137.
  8. L. Bozgeyikli, E. Bozgeyikli, A. Raij, R. Alqasemi, S. Katkoori, and R. Dubey,
    “Vocational Training with Immersive Virtual Reality for Individuals with
    Autism: Towards Better Design Practices,” In IEEE 2nd Workshop on Everyday Virtual Reality (WEVR), Greenville, SC, 2016, Page(s): 21-25.
  9. L. Bozgeyikli, A. Raij, S. Katkoori, and R. Alqasemi, “Effects of Environmental Clutter and Motion on User Performance in Virtual Reality Game,” In Proceedings of ACM SIGCHI Annual Symposium on Computer-Human Interaction in Play (CHI PLAY) Workshop on Fictional Game Elements: Critical Perspectives on Gamification Design. CEUR Workshop Proceedings, Vol-1715, 2016.
  10. S. Aditham, N. Ranganathan and S. Katkoori, “Memory access pattern based insider threat detection in big data systems,” 2016 IEEE International Conference on Big Data (Big Data), Washington, DC, 2016, Page(s): 3625-3628.
  11. L. Bozgeyikli, A. Raij, S. Katkoori, and R. Alqasemi. “Effects of Visual Fidelity and View Zoom on Task Performance in Virtual Reality,” In Proceedings of The 13th Annual Conference of the European Association for Virtual Reality and Augmented Reality (EuroVR), November 2016.
  12. O. Dokur, N. Elmehraz, and S. Katkoori, “Embedded System Design of a Real-time Parking Guidance System,” 2016 Annual IEEE Systems Conference (SysCon), Orlando March 2016, Pages: 1-8.
  13. S. Pendyala and S. Katkoori, “State Encoding based NBTI Optimization in Finite State Machines,” 2016 International Symposium on Quality of Electronic Design (ISQED), March 2016, Page(s): 416-422.
  14. R. P. O’Brien, S. Katkoori, M. A. Rowe, “Design and Implementation of an Embedded System for Monitoring At-home Solitary Alzheimer’s Patients,” 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2-5 Aug. 2015, Page(s):1-4.
  15. S. Pendyala and S. Katkoori, “Self Similarity and Interval Arithmetic Based Leakage Optimization in RTL Datapaths,” 2014 IEEE/IFIP 22nd International Conference on VLSI and System-on-Chip (VLSI-SoC), Oct. 2014. Best Paper Candidate (5 best paper nominations. 31 full papers accepted out of 104 regular submission). Invited for a Springer Book Chapter.
  16. M. Johnson, A. Fabregas, Z. Wang, S. Katkoori, and P-S. Lin, “Embedded System Design of an Advanced Illumination Measurement System for Highways,” 8th Annual IEEE Systems Conference (SysCon), 2014, Page(s): 579 – 586.
  17. N. Elmehraz, S. Katkoori, A. Kourtellis, and P-S. Lin, “Prototyping of a Portable Data Logging Embedded System for Naturalistic Motorcycle Study,” International Conference on
    Connected Vehicles and Expo (ICCVE), 2013. Page(s): 471 – 472.
  18. C. Bell, M. Lewandowski, S. Katkoori, “A Multi-parameter Functional Side-channel Analysis Method for Hardware Trust Verification,” IEEE 31st VLSI Test Symposium (VTS), 2013, Page(s) 1-4.
  19. I. Bahar, A. K. Jones, S. Katkoori, P. H. Madden, D. Marculescu, and I. L. Markov, “Scaling the impact of EDA education — Preliminary findings from the CCC workshop series on extreme scale design automation,” 2013 IEEE International Conference on Microlectronic Systems Education (MSE), 2013, Page(s): 64-67.
  20. C. S. Paidimarry, B. P. Kumar, and S. Katkoori, “A Novel Approach to Crosstalk Noise Analysis in CMOS Inverter driven Coupled RLC Interconnects,” 2013 Annual IEEE India Conference (INDICON), 2013, Page(s): 1-6.
  21. M. Lewandowski, R. Meana, M. Morrison, and S. Katkoori,  “A Novel Method for Watermarking Sequential Circuits,” 2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), June 2012, Page(s): 21-24.
  22. S. Pendyala and S. Katkoori, “Interval arithmetic based input vector control for RTL subthreshold leakage minimization,” 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), Oct. 2012, Page(s): 141-146.
  23. S. Roy, N. Ranganathan, and S. Katkoori, “Compiler Directed Power Gating in Embedded Microprocessors,” IEEE International Conference on Computer Design (ICCD), October 2009, Page(s): 35-40.
  24. S. Roy, N. Ranganathan, and S.Katkoori, “Exploration of Compiler Optimization Techniques for Enhancing Power Gating,” IEEE International Symposium on Circuits and Systems (ISCAS),  May 2009, Page(s): 1004-1007.
  25. H. Sankaran and S. Katkoori, “Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs,” IEEECS Annual Symposium on VLSI (ISVLSI), May 2009, Page(s): 274 – 279.
  26. H. Sankaran and S. Katkoori, “On-chip Dynamic Worst-case Crosstalk Pattern Detection and Elimination for Bus-based Macro-cell Designs,” International Symposium on Quality Electronic Design (ISQED), March 2009, Page(s): 33 – 39.
  27. V. Krishnan and S. Katkoori, “Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis,” 22nd International Conference on VLSI Design (VLSID), January 2009, Page(s): 419 – 424.
  28. H. Sankaran and S. Katkoori, “Simultaneous Scheduling, Allocation, Binding, Re-ordering, and  Encoding for Crosstalk Pattern Minimization during High Level Synthesis,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2008, Page(s): 423 – 428.
  29. H. Sankaran and S. Katkoori,  “Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis,” 4th IEEE Symposium on Electronic Design, Test, and Applications (DELTA), January 2008, Page(s): 454 – 457.
  30. P. Fernando, H. Sankaran, S. Katkoori, D. Keymeulen, A. Stoica, R. Zebulum, R. Ramesham “A Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine,” IEEE International Symposium on Parallel and Distributed Processing (IPDPS) 2008, April 2008, Page(s): 1 – 8.
  31. V. Krishnan and S. Katkoori, “A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits,” 8th International Symposium on Quality Electronic Design (ISQED), March 2007, Page(s): 885–892.
  32. V. Krishnan and S. Katkoori, “Minimizing Wire Delays by Net-topology Aware Binding during Floorplan-driven High Level Synthesis,”  2007 IFIP International Conference on Very Large Scale Integration (VLSI-SOC), October 2007, Page(s):99-104.
  33. P. Fernando and S. Katkoori, “An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning,” 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 337 – 342.
  34. V. Krishnan and S. Katkoori “Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis,” 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 641 – 646.
  35. A. Stoica, R. Zebulum, D. Keymeulen, R. Ramesham, J. Neff, and S. Katkoori, “Temperature-Adaptive Circuits on Reconfigurable Analog Arrays,” IEEE Aerospace Conference, March 2007, Page(s): 1 – 6. (No hardcopy proceedings.)
  36. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, “Extreme Temperature Electronics based on Self-Adaptive System using Field Programmable Gate Array,” IEEE Aerospace Conference, March 2007, Page(s):1 – 6.  (No hardcopy proceedings.)
  37. W. Alvis, W.; S. Murthy, K. Valavanis, W. Moreno, M. Fields, and S. Katkoori, “FPGA based Flexible Autopilot Platform for Unmanned Systems,” 2007 Mediterranean Conference on Control & Automation (MED), June, 2007, Page(s): 1 – 9.
  38. S. Roy, S. Katkoori, and N. Ranganathan, “A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors,” 20th International Conference on VLSI Design (VLSID), January 2007, Page(s): 215-220.
  39. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, “Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics,” First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):296 – 300.
  40. A. Stoica, R. S. Zebulum, D. Keymeulen, R. Ramesham, J. Neff, and S. Katkoori, “Temperature-Adaptive Circuits on Reconfigurable Analog Arrays,” First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):28 – 31.
  41. V. Krishnan and S. Katkoori, “Design Space Exploration of RTL Datapaths using Rent Parameter based Stochastic Wirelength Estimation,” 7th International Symposium on Quality Electronic Design (ISQED), March 2006, Page(s): 363 – 369.
  42. R. Gopalan, C. Gopalakrishnan, and S. Katkoori, “Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 2005, Page(s):167 – 172.
  43. H. Sankaran, S. Katkoori, and U. Kailasam, “System Level Energy Optimization for Location-Aware Computing,” IEEE Conference on Pervasive Computing (PerCom), March 2005, Page(s):319 – 323.
  44. H. Li, S. Katkoori, and Z. Liu, “Feedback Driven High Level Synthesis for Performance Optimization,” 6th International Conference On ASIC (ASICON), Volume 2, October 2005, Page(s): 961 – 964.
  45. H. Li, S. Katkoori, and W-K. Mak, “Force-Directed Performance Driven Placement Algorithm for FPGAs,” Proceedings of IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s):193 – 198.
  46. C. Gopalakrishnan and S. Katkoori, “Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths,” IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s): 260 – 261.
  47. S. Gupta and S. Katkoori, “A Fast Word-Level Estimation Technique for Intra-Crosstalk,” Design, Automation and Test in Europe (DATE) Conference, Volume 2, February 2004, Page(s): 1110-1115.
  48. S. Alupoaei and S. Katkoori, “Energy Model Based Macrocell Placement for Wirelength Minimization,” Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 713 – 716.
  49. S. Alupoaei and S. Katkoori, “Ant Colony Optimization Technique for Macrocell Overlap Removal,” Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 963 – 968.
  50. S. Gupta and S. Katkoori, “Intra-Bus Crosstalk Estimation Using Word-Level Statistics,” Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 449 – 454.
  51. C. Gopalakrishnan and S. Katkoori, “KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths,” Proceedings of 21st International Conference on Computer Design (ICCD), October 2003, Page(s): 430 – 435.
  52. C. Gopalakrishnan and S. Katkoori, “A Fast Hierarchical Leakage Power Simulator for VHDL Structural Descriptions,” IEEE Computer Society Symposium on VLSI (ISVLSI), February 2003, Page(s): 211-212.
  53. H. Li, W. K. Mak, and S. Katkoori, “An Efficient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization,” Asia-Pacific Design Automation Conference (ASPDAC), January 2003, Page(s): 353-358. Nominated for Best Paper Award.
  54. C. Gopalakrishnan and S. Katkoori, “Resource Allocation and Binding for Low Leakage Power,” 16th International Conference on VLSI Design (VLSID), January 2003, Page(s): 297-302.
  55. C. Gopalakrishnan and S. Katkoori, “Behavioral Synthesis of Datapaths with Low Leakage Power,” IEEE International Symposium on Circuits and Systems (ISCAS), Volume: 4, May 2002, Page(s): 699 -702.
  56. S. Gupta and S. Katkoori, “Force-directed Scheduling for Dynamic Power Optimization,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2002, Page(s): 68-73.
  57. C. Gopalakrishnan and S. Katkoori, “Power Optimization using Input Transformations,” First IEEE Intl. Workshop on Electronic Design, Test, & Applications (DELTA), January 2002, Page(s): 154-158.
  58. S. Alupoaei and S. Katkoori, “Net Clustering Based Macro-cell Placement,” 15th International Conference on VLSI Design (VLSID), January 2002, Page(s): 399-404.
  59. H. Li, W. K. Mak, S. Katkoori, “Low Power Mapping for FPGAs with Optimal Depth,” IEEE Computer Society Workshop on VLSI (WVLSI), April 2001, Page(s): 123-128.
  60. S. Katkoori and S. Alupoaei, “RT-level Interconnect Optimization in DSM Regime,” IEEE Computer Society Workshop on VLSI (WVLSI), April 2000, Page(s): 143-148.
  61. S. Katkoori and R. Vemuri, “Scheduling for Low Power under Resource and Latency Constraints,” International Symposium on Circuits and Systems (ISCAS), May 2000, Vol. 2, Page(s): 53-56.
  62. A. Durbha and S. Katkoori, “Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime,” X IFIP International Conference on Very Large Scale Integration (IFIP VLSI), December 1999, Page(s): 427-438.
  63. P. Maurer, S. Katkoori, W. Mak, M. Varanasi, “Component-Level Programming: A Revolution in Software Technology,”  Proceedings of the Frontiers in Education Conference, Proceedings of the 29th Annual Frontiers in Education Conference, Volume 2, November 1999, Page(s): 12B1/11 -12B1/15.
  64. S. Katkoori and R. Vemuri, “Accurate Resource Estimation Algorithms for Behavioral Synthesis,” Great Lakes Symposium on VLSI Conference (GLSVLSI), March 1999, Page(s): 338-339.
  65. V. Natesan, A. Gupta, S. Katkoori, D. Bhatia, and R. Vemuri, “A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis,” Asia and South-Pacific Design Automation Conference (ASPDAC), January 1997, Page(s): 509 – 515.
  66. S. Katkoori and R. Vemuri, “Simulation Based Architectural Power Estimation for PLA-Based Controllers,” International Symposium on Low Power and Electronic Design (ISLPED), August 1996, Page(s): 121-124.
  67. S. Katkoori, J. Roy, and R. Vemuri, “A Hierarchical Register Optimization Algorithm for Behavioral Synthesis,” 9th International Conference on VLSI Design (VLSID), January 1996, Page(s): 126-134.
  68. S. Katkoori and R. Vemuri, “A Power Simulator for VHDL Structural Descriptions,” VHDL International User’s Forum (VIUF) Fall Conference, October 1995, Page(s): 4.17-4.25.
  69. S. Katkoori, N. Kumar and R. Vemuri, “High Level Profiling Based Low Power Synthesis Technique,” International Conference on Computer Design (ICCD), October 1995, Page(s): 446-452.
  70. S. Katkoori, N. Kumar, L. Rader and R. Vemuri, “A Profile Driven Approach for Low Power Synthesis,” IFIP Intl. Conference on VLSI Design (VLSID), August 1995, Page(s): 759-765.
  71. D. Bhatia, R. Rajagopalan, and S. Katkoori, “Hierarchical Reconfiguration of VLSI/WSI Arrays,” 7th International Conference on VLSI Design (VLSID), January 1994, Page(s): 349-352.